What’s due

1. HDL: As with prior assignments, your completed HDL needs to be submitted (via GitHub) to Gradescope. A significant portion of the grade comes from passing unit tests.
2. Questions: The GitHub submission needs to include completed answer to the questions in questions.md in the repo.
3. Demo: An in-person demo is required for part of the grade. The demo needs to be completed during office hours (instructor or TA hours) within 10 days after the assignment is officially due. Normally this would put the deadline on March 11th, which is during spring break. The “workday count” is suspended during break. Consequently, the demos on this assignment must be completed by the end of Thursday, March 19th. Late penalties are based on the Gradescope submission, not the completion of the demo.

Setup

Create a Repo

1. Navigate to link
2. If shown a list of IDs, select your WUSTL Key from the list (this only needs to be done once. If you already did this during studio, you won’t be given the optiona gain)
   
3. “Accept the assignment”.
   

4. Follow the link to the new repository for the group:
   

   Setup Caution!

   The first time you do this you may be told that there is a Repository Access Issue. This is often because you have been “invited” to join our class organization and haven’t yet accepted the invitation. Either:

   • Check the email address associated with your GitHub account — you should have an email with an offer to join the course’s organization or
   • Update the Update/use this URL to view and accept the invitation. Be sure to change the “GITHUBUSER” part of the URL to your username: https://github.com/WashU-CSE2600-SP26/homework-4a-GITHUBUSER/invitations (E.g., if your GitHub username were washubear, the URL you’d use would be https://github.com/WashU-CSE2600-SP26/homework-4a-washubear/invitations)

Codespaces

1. We’ll be using Codespaces for many studios and assignments.
2. Create a code space from the repository:
   

Problem 1: Your assignment: Simple Combinational Logic

1. Run the 1.1 simple_comb testbench verification task (Click the VSCode Tasks icon on the side bar () and then the task’s name). Observe that the PROBLEMS tab shows that several test cases failed:

   

2. The “Vaporview” pane will allow you to explore signals that were being used in the test. You will need to Add signals from the Netlist View (the wires / variables in the HDL) and will probably want to always enable Auto Reload.

   

   Expand the simple_comb_tb (this is the test bench), then the dut (the “device under test”), then select variables a, b, and c:

   

3. Notice the picture above only shows the initial values of a, b, and c but you should be able to see the full signal (zoom to fit, or zoom in/out, or scroll). If you click the mouse along the signal it will show you the values of each at exactly that instant. Or if you click and drag you can see how they change as time changes. Review them from the beginning (t=0) to the end (t=175).

4. Run the 0.0 Edit questions.md task and answer question 1 in the designated place (don’t remove the # Q lines!, but remove/replace the TODO lines. You can answer with plain text, although you are also welcome to use MarkDown notation for styling if you’d like).

5. Run the 1.2 Edit simple_comb.sv task. Review the description of what’s expected and fix the designated line using basic Verilog operations (behavioral Verilog with symbols for the operations, like & for AND).

6. Re-run 1.1 simple_comb testbench verification and confirm that all tests pass in the PROBLEMS pane. (Or, if not, continue to edit simple_comb.sv).

7. Once it correctly passes the test bench, run ask 1.3 Simulate simple_comb.sv, which will allow you to simulate the circuit. Be sure to hit the "play" button in the DIGITALJS: CONTROL` pane to simulate the circuit.

   Caution!

   This “gate level” simulation does not consistently refresh the view if/when you update the underlying code. Be sure to close this form of simulation before re-running it!

8. Set c to a 1 and both a and b to 0.

9. Complete Q2 in questions.md.

10. The “synthesis” takes our HDL description and breaks it down into simpler parts which can be run on real hardware. Run task 1.4 AIG Mapping. Complete Q3 and Q4 in questions.md. If the results look like empty, You may have to pan/scroll around to see the graph generated by the AIG mapping.

Problem 2: Verilog Structure

Consider the circuit:

1. Use task 2.1 Edit structural.sv and complete the HDL description using structural modeling!

   Primitive gates can be modeled with the format: type(output, inputs...). For example, a 3-input or gate could be modeled with or(output, a, b, c); or with a unique name for the instance of the or gate, like or gate1(out, a, b, c);.

   Beware!

   For most of the semester we will use SystemVerilog’s logic type, which can represent either a connection between elements or a value stored (latched or in a flip-flop). There are cases, including here, where a wire type needs to be used to represent a true wire.
   

   The simulator for the test bench is very strict about this and will require the output of primitive, structural gates be an appropriate type, like wire.
   

   The simple simulator is much less rigid. It makes some assumptions about default behavior and will simulate things that are not defined precisely enough for the simulator.
   

   The difference in behavior between different tools is partly a result of their different intended uses and partly a result of how rigidly they enforce standards.

   Caution!

   The problem asks for a structural model. You should not use always_comb statements. assign should only be used for the final, simple assignments of outputs (of the format assign output = internal. They should not use more complex expressions.) You should use the primitive parts and(...), or(...), not(...), etc. Although you may pass test cases with other forms of modeling, credit will only be given for a structural model.

2. Use the 2.2 Simulate structural.sv task and the 2.5 structural testbench tasks to test your work. Revise your work until you pass the testbench (but, again, be sure you are using ONLY structural elements. No use of operators like ~, ^, &, etc.)

3. Run task 2.4 (AIG Mapping) and 2.5 (iCE40 Mapping) and answer Q5 in questions.md.

Problem 3: Basic addition - Revisiting Hw 2a

Consider adding 2-digit binary numbers, $a$ and $b$ to produce the 2-bit result, $s$ and a one-bit carry-out, $c$:

1. Use task 3.1 to edit add2.sv. Complete it as described. Use tasks 3.2 and 3.3 to test your work. Update it until you pass all tests.
   • Task 3.2 Simulate add2.sv will allow you to simulate the adder. The inputs and outputs are no longer simple, binary value. Hovering over an input or output will allow you to use the base being used to enter or show that value:

   

   Caution!

   You must update values and then click out of the input box for the simulator to use the updated value. (If the cursor is still in the box, it isn’t clear that you are done typing a new value)

   • Task 3.3 add2 testbench verification will allow you to run a comprehensive testbench against the adder. Make sure your adder passes the tests.

2. Use the 3.4 add2 AIG Mapping and 3.5 add2 iCE40 Mapping to get a sense of how your approach is represented in individual logic operations vs. how it will use the iCE40 logic blocks, which are like small look-up tables (LUTs) that can be used to implement a variety of simple logic operations.

3. Use 3.6 add2 iCE40 bitstream to create a bit stream and Program your Device. (This requires running the FPGA Image Server task first. The FPGA Image Server will continue to run until you hit it’s task again to end it. Leave it running.)
   • The left four buttons can be used to increase or decrease the values used for a and b, which are displayed in the designaed aresa.
   • s, the sum, will be shown on the rightmost digit.
   • c, the carry out, will be shown on the decimal point of the second digit from the right.

1. Use the 3.7 iCE40 Routing (This requires that the FPGA Server task is running and will open a new webpage. It may also take some time to run). This can give to get a sense of what resources are used for your adder and the interface to the external hardware. Expand the sections and try to identify the percentage of logic cells (LCs) being used. You can use Open Image to browse a large picture of how the blocks inside the iCE40 are being used and connected for this project. It’s a large grid of blocks and you may have to pan/scroll to find blocks that are being used, which have red-shaded lines.

2. Complete Q7-Q13 in questions.md

End of work

Submission

The assignment will be submitted via GitHub and Gradescope.

1. First, be sure to commit and push files to GitHub (as shown in studio).

1.1

1.2

1.3

2. Then go to GitHub.com and confirm the updates are on GitHub

3. Finally (after confirming updates are on GitHub), go to the assignment in Gradescope and import it from GitHub:

3.1

3.2

• Submission Link: Gradescope