Scope

The intent of this final homework/project is to combine and demonstrate your understanding of digital logic concepts.

It’s a creative project — you can create anything you want, but the expectations are:

1. It needs be a moderate, new digital logic creation (i.e., your work and non-trivial and digital logic).
2. The bulk of the significant work needs to be solely yours. You should be able to explain details of how it works.
   1. You may use modules from class to support your work.
   2. You may use other (non-class) modules if you get advanced permission. To get permission create a Private post on Piazza to instructors to explain: what you want to do, how the module(s) help(s), and cite the module.
3. It needs to be reasonably distinct from prior course work. For example, a simple state machine that is comparable to the washer may be eligible for some credit, but not full credit unless there are substantial additions. (I.e., derivative works are a way to get some additional experience with Digital Logic, but don’t really demonstrate your ability to apply course ideas to new problems!)
4. It needs to run on the FPGA hardware for full credit.

Acceptable Examples

1. Games (implemented via direct Digital Logic)

   Pong, the first commercially successful video game, was built directly from digital logic. Although using 8, 7-segment displays and 8 buttons is a bit limited, you may be able to come up with some interesting games.

2. An new CPU!

   The AVR microcontroller commonly sued in Arduinos was a student project for an M.S. Thesis project ( Story here and here (by one of the co-developers)). You don’t have to develop anything nearly as complex as the RISC-V (or AVR), but a processor with a 4-10 instructions to do a combination of data manipulation, data movement, and control, is sufficient.

3. Significant, digital logic extension to the RISC-V model used in class are allowed. For example, you could add support some new piece of hardware, like an LCD screen, and demonstrate that support using a little RISC-V code. The focus should be on supporting new hardware. (See above: Be sure to get in-advance permission to use external hardware)

4. Other ????

   We’re open to other digital logic creations, including some things that interface to external hardware. However, please open a private post on Piazza (instructors or just Profs. Hall & Siever) to discuss other ideas. Please have your idea reviewed/approved before starting on it, especially if you are attaching hardware!

Due Date

All work should be completed by 11:59pm on Friday, April 24th, but will be accepted late with no penalty until 11:59pm, Wednesday, April 29th. Work’s submission time will be based on when it’s put on Gradescope. Demos must be completed by 4pm on Wednesday, May 6th.

Demos are mandatory for credit.

Demos can be done during instructor office hours on/after May 20th. Additional office hours will be posted on April 20th. Remote demos will be allowed after April 24th if absolutely necessary, like if there are prior travel plans that require leaving the area before the 29th.

Submission

1. You need to give a demo to either Professor Hall or Professor Siever. (Live, in-person strongly preferred. Zoom-based demos will be allowed to compensate for prior travel plans that make in-person demos impossible)
2. The final work needs to be submitted/committed to Gradescope.
3. You need to complete the usual questions.md in the repo to summarize your work.

Resources

The link to create a repo: link

• Files & Folders: An overview of how files and folders are used to create projects.

Overview / Container Demo

Minor updates and additions to the video:

• CSE 2600 is using a custom fork of “Tasks in Sidebar” that will (now) automatically reload when the tasks are rebuild. (There’s no longer a Reload Tasks button in the list of tasks because it’s done automatically when one does Rebuild Tasks)
• The repo’s common folder includes a few modules:
  • ledandkey.sv is the I/O board support. It provides inputs for the buttons and outputs for each segment/LED. This is used in Homework 4A, 4B, 5, and 7A.
  • spinner.sv will do the “spinner” effect on a single 7-segment display. It was used in Homework 4B. It uses the ledandkey module.
  • digit_select.sv uses two buttons and a 7-segment display to allow users to select a nibble value (increase and decrease the displayed value). This was used in homework 5 (ALU project) to select values for testing. It also uses the ledandkey module.
  • timed_enable.sv this module allows one to “reduce” a clock to a slower clock. This was used in Homework 5 to slow the 6MHz clock to a rate that was reasonable to simultate the wash cycles.
  • pins.pcf specifies how names, like tm_clock, in the top most module are connected to the outside world (i.e., which pin they should connect to). It was present in all homeworks.

For each of the above you can look in the top.sv file of prior assignments to get a sense of how they may be used.

Submission

Be sure to commit/push all work, including a completed questions.md, to Gradescope (via GitHub).